View AD9278-BBCZ_6921264.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

octal lna/vga/aaf/adc and cw i/q demodulator ad9278 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 8 channels of lna, vga, aaf, adc, and i/q demodulator low power: 88 mw per channel, tgc mode, 40 msps; 32 mw per channel, cw mode 10 mm 10 mm, 144-ball csp-bga tgc channel input-referred noise: 1.3 nv/ hz, max gain flexible power-down modes fast recovery from low power standby mode: <2 s overload recovery: <10 ns low noise preamplifier (lna) input-referred noise: 1.25 nv/hz, gain = 21.3 db programmable gain: 15.6 db/17.9 db/21.3 db 0.1 db compression: 1000 mv p-p/ 750 mv p-p/450 mv p-p dual-mode active input impedance matching bandwidth (bw): >50 mhz variable gain amplifier (vga) attenuator range: ?45 db to 0 db postamp gain (pga): 21 db/24 db/27 db/30 db linear-in-db gain control antialiasing filter (aaf) programmable second-order lpf from 8 mhz to 18 mhz programmable hpf analog-to-digital converter (adc) snr: 70 db, 12 bits up to 50 msps serial lvds (ansi-644, low power/reduced signal) cw mode i/q demodulator individual programmable phase rotation output dynamic range per channel: >158 dbc/hz output-referred snr: 153 dbc/ hz, 1 khz offset, ?3 dbfs general description the ad9278 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. it contains eight channels of a variable gain amplifier (vga) with a low noise preamplifier (lna), an antialiasing filter (aaf), an analog-to-digital converter (adc), and an i/q demodulator with programmable phase rotation. each channel features a variable gain range of 45 db, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 51 db. the channel is optimized for high dynamic performance and low power in applications where a small package size is critical. the lna has a single-ended-to-differential gain that is selectable through the spi. assuming a 15 mhz noise bandwidth (nbw) and a 21.3 db lna gain, the lna input snr is roughly 88 db. in cw doppler mode, each lna output drives an i/q demod- ulator that has independently programmable phase rotation with 16 phase settings. power-down of individual channels is supported to increase battery life for portable applications. standby mode allows quick power-up for power cycling. in cw doppler operation, the vga, aaf, and adc are powered down. the adc contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. the digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface. functional block diagram aaf 12-bit adc vga lna serial lvds i/q demodulator 8 channels serial port interface data rate multiplier reference lo generation lo-a to lo-h losw-a to losw-h li-a to li-h lg-a to lg-h douta+ to douth+ douta? to douth? fco+ drvdd clk? clk+ sdio sclk csb gpo[0:3] rbias vref cwq+ cwq? cwi+ cwi? gain? gain+ 4lo? 4lo+ reset stb y pdwn a vdd2 a vdd1 fco? dco+ dco? 09424-001 figure 1.
ad9278 rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? ac specifications.......................................................................... 3 ? digital specifications ................................................................... 6 ? switching specifications .............................................................. 7 ? adc timing diagrams ............................................................... 8 ? absolute maximum ratings............................................................ 9 ? thermal impedance ..................................................................... 9 ? esd caution.................................................................................. 9 ? pin configuration and function descriptions........................... 10 ? typical performance characteristics ........................................... 13 ? tgc mode................................................................................... 13 ? cw doppler mode..................................................................... 16 ? equivalent circuits......................................................................... 17 ? ultrasound theory of operation ................................................. 19 ? channel overview.......................................................................... 20 ? tgc operation........................................................................... 20 ? cw doppler operation............................................................. 33 ? serial port interface (spi).............................................................. 37 ? hardware interface..................................................................... 37 ? memory map .................................................................................. 39 ? reading the memory map table.............................................. 39 ? reserved locations .................................................................... 39 ? default values ............................................................................. 39 ? logic levels................................................................................. 39 ? outline dimensions ....................................................................... 43 ? ordering guide .......................................................................... 43 ? revision history 10/10revision 0: initial version
ad9278 rev. 0 | page 3 of 44 specifications ac specifications avdd1 = 1.8 v, avdd2 = 3.0 v, drvdd = 1.8 v, 1.0 v internal adc reference, full temperature range (?40c to +85c), f in = 5 mhz, r s = 50 , r fb = (unterminated), lna gain = 21.3 db, lna bias = default, pga gain = 24 db, gain? = 0.8 v, gain+ = 0 v, aaf lpf cutoff = f sample /3 (mode i/ii/iii), hpf cutoff = lpf cutoff/12, mode i = f sample = 40 msps, mode ii = f sample = 25 msps, mode iii = f sample = 50 msps, low power lvds mode, unless otherwise noted. table 1. parameter 1 test conditions/comments min typ max unit lna characteristics gain single-ended input to differential output 15.6/17.9/21.3 db single-ended input to single-ended output 9.6/11.9/15.3 db 0.1 db input compression point lna gain = 15.6 db 1.00 v p-p lna gain = 17.9 db 0.75 v p-p lna gain = 21.3 db 0.45 v p-p 1 db input compression point lna gain = 15.6 db 1.20 v p-p lna gain = 17.9 db 0.90 v p-p lna gain = 21.3 db 0.60 v p-p input common mode (li-x, lg-x) 2.2 v output common mode (lo-x) v output common mode (losw-x) switch off high-z switch on 1.5 v input resistance (li-x) r fb = 350 , lna gain = 21.3 db 50 r fb = 1400 , lna gain = 21.3 db 200 r fb = , lna gain = 21.3 db 15 k input capacitance (li-x) 22 pf ?3 db bandwidth lna gain = 15.6 db 100 mhz lna gain = 17.9 db 80 mhz lna gain = 21.3 db 50 mhz input noise voltage r s = 0 , r fb = lna gain = 15.6 db 1.60 nv/hz lna gain = 17.9 db 1.42 nv/hz lna gain = 21.3 db 1.27 nv/hz input noise current r fb = 1.5 pa/hz noise figure r s = 50 active termination matched lna gain = 15.6 db, r fb = 200 7.8 db lna gain = 17.9 db, r fb = 250 6.7 db lna gain = 21.3 db, r fb = 350 5.6 db unterminated lna gain = 15.6 db, r fb = 6.1 db lna gain = 17.9 db, r fb = 5.3 db lna gain = 21.3 db, r fb = 4.7 db full-channel (tgc) characteristics aaf low-pass cutoff ?3 db, programmable 8 18 mhz in range aaf bandwidth tolerance 10 % group delay variation f = 1 mhz to 18 mhz, gain+ = 0 v to 1.6 v 0.3 ns
ad9278 rev. 0 | page 4 of 44 parameter 1 test conditions/comments min typ max unit input-referred noise voltage gain+ = 1.6 v, r fb = lna gain = 15.6 db 1.7 nv/hz lna gain = 17.9 db 1.5 nv/hz lna gain = 21.3 db 1.3 nv/hz noise figure gain+ = 1.6 v, r s = 50 active termination matched lna gain = 15.6 db, r fb = 200 9.2 db lna gain = 17.9 db, r fb = 250 7.7 db lna gain = 21.3 db, r fb = 350 6.3 db unterminated lna gain = 15.6 db, r fb = 6.7 db lna gain = 17.9 db, r fb = 5.7 db lna gain = 21.3 db, r fb = 4.9 db correlated noise ratio no signal, correlated/uncorrelated ?30 db output offset ?35 +35 lsb signal-to-noise ratio (snr) f in = 5 mhz at ?10 dbfs, gain+ = 0 v, 65 dbfs f in = 5 mhz at ?1 dbfs, gain+ = 1.6 v 57 dbfs harmonic distortion second harmonic f in = 5 mhz at ?10 dbfs, gain+ = 0 v ?70 dbc f in = 5 mhz at ?1 dbfs, gain+ = 1.6 v ?70 dbc third harmonic f in = 5 mhz at ?10 dbfs, gain+ = 0 v ?70 dbc f in = 5 mhz at ?1 dbfs, gain+ = 1.6 v ?70 dbc two-tone intermodulation (imd3) f rf1 = 5.015 mhz, f rf2 = 5.020 mhz, a rf1 = 0 db, a rf2 = ?20 db, gain+ = 1.6 vimd3 relative to a rf2 ?70 dbc channel-to-channel crosstalk f in1 = 5.0 mhz at ?1 dbfs ?60 db overrange condition 2 ?55 db channel-to-channel delay variation full tgc path, f in = 5 mhz, gain+ = 0 v to 1.6 v 0.3 degrees pga gain differential input to di fferential output 21/24/27/30 db gain accuracy 25c gain law conformance error 0 < gain+ < 0.16 v 0.5 db 0.16 v < gain+ < 1.44 v ?1.6 +1.6 db 1.44 v < gain+ < 1.6 v 0.5 db linear gain error gain+ = 0.8 v, normalized for ideal aaf loss ?1.6 +1.6 db channel-to-channel matching 0.16 v < gain+ < 1.44 v 0.1 db gain control interface control range differential ?0.8 +0.8 v single-ended 0 1.6 v gain range gain+ = 0 v to 1.6 v 45 db scale factor 28 db/v response time 45 db change 750 ns gain+ impedance single-ended 10 m gain? impedance single-ended 70 k cw doppler mode lo frequency f lo = f 4lo /4 1 10 mhz phase resolution per channel 22.5 degrees output dc bias (single-ended) cwi+, cwi?, cwq+, cwq? 1.5 v output ac current range per cwi+, cwi?, cwq+, cwq?, each channel enabled 1.25 ma transconductance (differential) demodulated i out /v in , per cwi+, cwi?, cwq+, cwq? lna gain = 15.6 db 1.8 ma/v lna gain = 17.9 db 2.4 ma/v lna gain = 21.3 db 3.5 ma/v
ad9278 rev. 0 | page 5 of 44 parameter 1 test conditions/comments min typ max unit input-referred noise voltage r s = 0 , r fb = lna gain = 15.6 db 2.0 nv/hz lna gain = 17.9 db 1.9 nv/hz lna gain = 21.3 db 1.8 nv/hz noise figure r s = 50 , r fb = lna gain = 15.6 db 7.8 db lna gain = 17.9 db 7.3 db lna gain = 21.3 db 6.9 db input-referred dynamic range r s = 0 , r fb = lna gain = 15.6 db 162 dbfs/hz lna gain = 17.9 db 160 dbfs/hz lna gain = 21.3 db 157 dbfs/hz output-referred snr ?3 dbfs input, f rf = 2.5 mhz, f 4lo = 10 mhz, 1 khz offset 153 dbc/hz two-tone intermodulation (imd3) f rf1 = 5.015 mhz, f rf2 = 5.020 mhz, f 4lo = 20 mhz, a rf1 = ?1 dbfs, a rf2 = ?21 dbfs, imd3 relative to a rf2 ?58 db quadrature phase error i to q, all phases, 1 0.15 degrees i/q amplitude imbalance i to q, all phases, 1 0.015 db channel-to-channel matching phase i to i, q to q, 1 0.5 degrees amplitude i to i, q to q, 1 0.25 db power supply, mode i/ii/iii avdd1 1.7 1.8 1.9 v avdd2 3 2.7 3.0 3.6 v drvdd 1.7 1.8 1.9 v i avdd1 tgc mode 178/145/215 ma cw doppler mode 32 ma i avdd2 tgc mode, no signal 108 ma cw doppler mode 63 ma i drvdd ansi-644 mode 47/44/48 ma low power (ieee 1596.3 similar) mode 33/31/34 total power dissipation (including output drivers) tgc mode, no signal 704/640/772 815/755/908 mw cw doppler mode 252 mw power-down dissipation 5 mw standby power dissipation 420 mw power supply rejection ratio (psrr) 1.6 mv/v adc resolution 12 bits adc reference output voltage error vref = 1 v 50 mv load regulation at 1.0 ma vref = 1 v 2 mv input resistance 6 k 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 the overrange condition is specified as 6 db more than the full-scale input range. 3 when the lna gain is set to 15.6 db, avdd2 > 3.0 v.
ad9278 rev. 0 | page 6 of 44 digital specifications avdd1 = 1.8 v, avdd2 = 3.0 v, drvdd = 1.8 v, 1.0 v internal adc reference, full temperature, unless otherwise noted. table 2. parameter 1 temperature min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 250 mv p-p input common-mode voltage full 1.2 v input resistance (differential) 25c 20 k input capacitance 25c 1.5 pf cw 4lo inputs (4lo+, 4lo?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 250 mv p-p input common-mode voltage full 1.2 v input resistance (differential) 25c 20 k input capacitance 25c 1.5 pf logic inputs (pdwn, stby, sclk, reset) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 30 k input capacitance 25c 0.5 pf logic input (csb) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 70 k input capacitance 25c 0.5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.2 drvdd + 0.3 v logic 0 voltage (i ol = 50 a) full 0 0.3 v input resistance 25c 30 input capacitance 25c 2 digital outputs (doutx+, doutx?), (ansi-644) logic compliance lvds differential output voltage (v od ) full 247 454 mv output offset voltage (v os ) full 1.125 1.375 v output coding (default) offset binary digital outputs (doutx+, doutx?), (low power, reduced signal option) logic compliance lvds differential output voltage (v od ) full 150 250 mv output offset voltage (v os ) full 1.10 1.30 v output coding (default) offset binary logic output (gpo0/gpo1/gpo2/gpo3) logic 0 voltage (i ol = 50 a) full 0.05 v 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 specified for lvds and lvpecl only. 3 specified for 13 sdio pins sharing the same connection.
ad9278 rev. 0 | page 7 of 44 switching specifications avdd1 = 1.8 v, avdd2 = 3.0 v, drvdd = 1.8 v, full temperature, unless otherwise noted. table 3. parameter 1 temperature min typ max unit clock 2 clock rate 25 msps (mode ii) full 18.5 25 mhz 40 msps (mode i) full 18.5 40 mhz 50 msps (mode iii) full 18.5 50 mhz clock pulse width high (t eh ) full 6.25 ns clock pulse width low (t el ) full 6.25 ns output parameters 2 , 3 propagation delay (t pd ) full (t sample /2) + 1.5 (t sample /2) + 2.3 (t sample /2) + 3.1 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full (t sample /2) + 1.5 (t sample /2) + 2.3 (t sample /2) + 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /24) ns dco to data delay (t data ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t frame ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data-to-data skew (t data-max ? t data-min ) full 100 350 ps wake-up time (standby), gain+ = 0.5 v 25c 2 s wake-up time (power-down) 25c 1 ms pipeline latency full 8 clock cycles aperture aperture uncertainty (jitter) 25c <1 ps rms lo generation 4lo frequency full 4 40 mhz lo divider reset setup time 5 full 5 ns lo divider reset hold time 5 full 5 ns lo divider reset high pulse width full 20 ns 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 can be adjusted via the spi. 3 measurements were made using a part soldered to fr-4 material. 4 t sample /24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 5 reset edge to rising 4lo edge.
ad9278 rev. 0 | page 8 of 44 adc timing diagrams dco? dco+ doutx? doutx+ fco? fco+ ain clk? clk+ msb n ? 8 d10 n ? 8 d9 n ? 8 d8 n ? 8 d7 n ? 8 d6 n ? 8 d5 n ? 8 d4 n ? 8 d3 n ? 8 d2 n ? 8 d1 n ? 8 d0 n ? 8 d10 n ? 7 msb n ? 7 n ? 1 n t data t frame t fco t pd t cpd t eh t el 09424-002 figure 2. 12-bit data serial stream (default) dco? dco+ doutx? doutx+ fco? fco+ ain clk? clk+ lsb n ? 8 d0 n ? 8 d1 n ? 8 d2 n ? 8 d3 n ? 8 d4 n ? 8 d5 n ? 8 d6 n ? 8 d7 n ? 8 d8 n ? 8 d9 n ? 8 d10 n ? 8 d0 n ? 7 lsb n ? 7 n ? 1 n t data t frame t fco t pd t cpd t eh t el 09424-003 figure 3. 12-bit data serial stream, lsb first
ad9278 rev. 0 | page 9 of 44 absolute maximum ratings table 4. parameter rating avdd1 to gnd ?0.3 v to +2.0 v avdd2 to gnd ?0.3 v to +3.9 v drvdd to gnd ?0.3 v to +2.0 v gnd to gnd ?0.3 v to +0.3 v avdd2 to avdd1 ?2.0 v to +3.9 v avdd1 to drvdd ?2.0 v to +2.0 v avdd2 to drvdd ?2.0 v to +3.9 v digital outputs (doutx+, doutx?, dco+, dco?, fco+, fco?) to gnd ?0.3 v to drvdd + 0.3 v clk+, clk?, sdio to gnd ?0.3 v to avdd1 + 0.3 v li-x, lo-x, losw-x to gnd ?0.3 v to avdd2 + 0.3 v cwi?, cwi+, cwq?, cwq+ to gnd ?0.3 v to avdd2 + 0.3 v pdwn, stby, sclk, csb to gnd ?0.3 v to avdd1 + 0.3 v gain+, gain?, reset, 4lo+, 4lo?, gpo0, gpo1, gpo2, gpo3 to gnd ?0.3 v to avdd2 + 0.3 v vref to gnd ?0.3 v to avdd1 + 0.3 v operating temperature range (ambient) ?40c to +85c storage temperature range (ambient) ?65c to +150c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impedance table 5. symbol description value 1 units ja junction-to-ambient thermal resistance, 0.0 m/s air flow per jedec jesd51-2 (still air) 22.0 c/w jb junction-to-board thermal characterization parameter, 0 m/s air flow per jedec jesd51-8 (still air) 9.2 c/w jt junction-to-top-of-package characterization parameter, 0 m/s air flow per jedec jesd51-2 (still air) 0.12 c/w 1 results are from simulations. pcb is jedec multilayer. thermal performance for actual applications re quires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. esd caution
ad9278 rev. 0 | page 10 of 44 pin configuration and fu nction descriptions 09424-004 1234 9101112 5678 a b c d e f g h j k l m li-e li-f li-g li-h li-a li-b li-c li-d vref rbias gain+ gain? lg-e lg-f lg-g lg-h lg-a lg-b lg-c lg-d gnd gnd avdd2 gnd lo-e lo-f lo-g lo-h lo-a lo-b lo-c lo-d gnd gnd gnd gnd losw-e losw-f losw-g losw-h losw-a losw-b losw-c losw-d gnd gnd gnd gnd gnd avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 gnd gnd gnd gnd gnd avdd1 gnd avdd1 gnd gnd avdd1 gnd avdd1 avdd1 gnd gnd avdd1 gnd avdd1 gnd avdd1 avdd1 gnd avdd1 gnd gnd gnd gnd gnd clk? gnd gnd gnd gnd gnd gnd csb gnd gnd gnd gnd clk+ gnd cwq+ gnd gpo3 gpo1 pdwn sdio cwi+ avdd2 4lo+ gnd gnd gnd cwq? gnd gpo2 gpo0 stby sclk cwi? avdd2 4lo? reset drvdd douth+ doutg+ doutf+ doutc+ doutb+ douta+ drvdd doute+ dco+ fco+ doutd+ gnd douth? doutg? doutf? doutc? doutb? douta? gnd doute? dco? fco? doutd? figure 4. pin configuration 09424-005 a b c d e f g j h k l m 2 6 10 12 4 8 1357 11 9 top view (not to scale) figure 5.
ad9278 rev. 0 | page 11 of 44 table 6. pin function descriptions pin no. name description b5, b6, b8, c5, c6, c7, c8, d5, d6, d7, d8, e1, e5, e6, e7, e8, e12, f2, f4, f6, f7, f9, f11, g1, g3, g5, g6, g7, g8, g10, g12, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11, j2, j4, j8, k1, k2, k4, m1, m12 gnd ground (should be tied to a quiet analog ground) f1, f3, f5, f8, f10, f12, g2, g4, g9, g11 avdd1 1.8 v analog supply b7, e2, e3, e4, e9, e10, e11, j6, k6 avdd2 3.0 v analog supply l1, l12 drvdd 1.8 v digital output driver supply a1 li-e lna analog input for channel e b1 lg-e lna ground for channel e c2 lo-f lna analog inverted output for channel f d2 losw-f lna analog switched output for channel f a2 li-f lna analog input for channel f b2 lg-f lna ground for channel f c3 lo-g lna analog inverted output for channel g d3 losw-g lna analog switched output for channel g a3 li-g lna analog input for channel g b3 lg-g lna ground for channel g c4 lo-h lna analog inverted output for channel h d4 losw-h lna analog switched output for channel h a4 li-h lna analog input for channel h b4 lg-h lna ground for channel h h1 clk? clock input complement j1 clk+ clock input true m2 douth? adc h digital output complement l2 douth+ adc h digital output true m3 doutg? adc g digital output complement l3 doutg+ adc g digital output true m4 doutf? adc f digital output complement l4 doutf+ adc f digital output true m5 doute? adc e digital output complement l5 doute+ adc e digital output true m6 dco? digital clock output complement l6 dco+ digital clock output true m7 fco? frame clock digital output complement l7 fco+ frame clock digital output true m8 doutd? adc d digital output complement l8 doutd+ adc d digital output true m9 doutc? adc c digital output complement l9 doutc+ adc c digital output true m10 doutb? adc b digital output complement l10 doutb+ adc b digital output true m11 douta? adc a digital output complement l11 douta+ adc a digital output true k11 stby standby power-down j11 pdwn full power-down k12 sclk serial clock j12 sdio serial data input/output h12 csb chip select bar b9 lg-a lna ground for channel a a9 li-a lna analog input for channel a d9 losw-a lna analog switched output for channel a c9 lo-a lna analog inverted output for channel a
ad9278 rev. 0 | page 12 of 44 pin no. name description b10 lg-b lna ground for channel b a10 li-b lna analog input for channel b d10 losw-b lna analog switched output for channel b c10 lo-b lna analog inverted output for channel b b11 lg-c lna ground for channel c a11 li-c lna analog input for channel c d11 losw-c lna analog switched output for channel c c11 lo-c lna analog inverted output for channel c b12 lg-d lna ground for channel d a12 li-d lna analog input for channel d d12 losw-d lna analog switched output for channel d c12 lo-d lna analog inverted output for channel d k10 gpo0 general purpose open drain output 0 j10 gpo1 general purpose open drain output 1 k9 gpo2 general purpose open drain output 2 j9 gpo3 general purpose open drain output 3 k8 reset reset for synchronizing 4lo divide-by-4 counter k7 4lo? cw doppler 4lo input complement j7 4lo+ cw doppler 4lo input true a8 gain? gain control voltage input complement a7 gain+ gain control voltage input true a6 rbias external resistor to set th e internal adc core bias current a5 vref voltage reference input/output k5 cwi? cw doppler i output complement j5 cwi+ cw doppler i output true k3 cwq? cw doppler q output complement j3 cwq+ cw doppler q output true c1 lo-e lna analog inverted output for channel e d1 losw-e lna analog switched output for channel e
ad9278 rev. 0 | page 13 of 44 typical performance characteristics tgc mode f sample = 40 msps, f in = 5 mhz, r s = 50 , lna gain = 21.3 db, lna bias = mid-high, pga gain = 24 db, gain? = 0.8 v, aaf lpf cutoff = f sample /3.0, hpf cutoff = lpf cutoff/12.00 (default). 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 gain+ (v) gain error (db) 09424-006 figure 6. gain error vs. gain+ 550 500 450 400 350 300 250 200 150 100 50 0 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 codes number of hits (thousands) 09424-007 1,000,000 total hits figure 7. output-referred noise histogram, gain+ = 0.0 v 220 240 200 180 160 140 120 100 80 60 40 20 0 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 codes number of hits (thousands) 09424-008 1,000,000 total hits figure 8. output-referred noise histogram, gain+ = 1.6 v 3.0 2.5 2.0 1.5 1.0 0.5 0 1234567 8910 frequency (mhz) input-referred noise (nv/ hz) 09424-072 figure 9. short-circuit, input- referred noise vs. frequency, lna gain = 21.3 db, pga gain = 30 db, gain+ = 1.6 v ? 128 ?130 ?132 ?134 ?136 ?138 ?140 ?142 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 gain+ (v) output-referred noise (dbfs/ hz) 09424-009 lna gain = 21.3db lna gain = 17.9db lna gain = 15.6db figure 10. short-circuit, output-referred noise vs. gain+ 64 66 62 60 58 56 54 52 50 1.0 0.4 0.6 0.8 1.2 1.4 1.6 gain+ (v) snr (dbfs) 09424-010 figure 11. snr vs. gain+, aout = ?1.0 dbfs
ad9278 rev. 0 | page 14 of 44 70 68 66 64 62 60 58 56 54 52 50 0.8 0 0.2 0.4 0.6 1.0 1.2 1.4 1.6 gain+ (v) snr/sinad (dbfs) 09424-011 snr sinad pga = 21db pga = 30db figure 12. snr/sinad vs. gain+, ain = ?45 dbm 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 02468101214161820 frequency (mhz) amplitude (dbfs) 09424-012 mode iii = 50msps mode ii = 25msps mode i = 40msps figure 13. antialiasing filter (aaf) pass-band response, lpf cutoff = 1 (1/3) f sample 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 0481 21 4 2 6 10 16 input frequency (mhz) second-order harmonic distortion (dbfs) 09424-013 gain+ = 1.6v gain+ = 1.0v gain+ = 0.4v figure 14. second-order harmonic distortion vs. frequency, aout = ?1.0 dbfs 0 ?10 ?20 ?30 ?40 ?60 ?70 ?80 ?50 0481 21 4 2 6 10 16 input frequency (mhz) third-order harmonic distortion (dbfs) 09424-014 gain+ = 1.6v gain+ = 1.0v gain+ = 0.4v figure 15. third-order harmonic distortion vs. frequency, aout = ?1.0 dbfs 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?40 ?30 ?20 ?10 ?5 ?35 ?25 ?15 0 adc output level (dbfs) second-order harmonic distortion (dbfs) 09424-015 gain+ = 1.4v gain+ = 0.8v figure 16. second-order harmonic distortion vs. adc output level, aout 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?40 ?30 ?20 ?10 ?5 ?35 ?25 ?15 0 adc output level (dbfs) third-order harmonic distortion (dbfs) 09424-016 gain+ = 1.4v gain+ = 0.8v figure 17. third-order harmonic distortion vs. adc output level
ad9278 rev. 0 | page 15 of 44 17.5 15.0 12.5 10.0 7.5 5.0 2.5 0 0 ?20 ?40 ?60 ?80 ?100 100k 1m 10m 100m frequency (hz) frequency (hz) phase (degrees) magnitude (k ? ) 09424-017 100k 1m 10m 100m figure 18. lna input impedance magnitude and phase, unterminated
ad9278 rev. 0 | page 16 of 44 cw doppler mode f in = 5 mhz, r s = 50 , lna gain = 21.3 db, lna bias = mid-high, all cw channels enabled, phase rotation 0 degrees. 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 100 1k 10k baseband frequency (hz) quadrature phase error (degrees) 09424-018 figure 19. quadrature (i/q) phase error vs. baseband frequency 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 100 1k 10k baseband frequency (hz) i/q amplitude imbalance (db) 09424-019 figure 20. quadrature (i/q) amplitude error vs. baseband frequency 12 10 8 6 4 2 0 0 1000 10,000 2000 3000 4000 5000 6000 7000 8000 9000 baseband frequency (hz) noise figure (db) 09424-020 figure 21. noise figure vs. baseband frequency
ad9278 rev. 0 | page 17 of 44 equivalent circuits li- x, lg- x avdd2 15k ? v cm 09424-022 figure 22. equivalent lna input ci rcuit (vcm = common-mode voltage) lo-x, losw-x 10? avdd2 avdd2 09424-023 figure 23. equivalent lna output circuit 350 ? 10k? 10k? clk? 350? 1.25v clk+ 09424-024 avdd1 avdd1 figure 24. equivalent clock input circuit 350 ? 10k? 10k? 4lo? 350? 1.25v 4lo+ 09424-025 avdd2 avdd2 figure 25. equivalent 4lo input circuit 09424-026 s dio 350? 30k ? a vdd1 figure 26. equivalent sdio input circuit dr v dd gnd drvdd doutx? doutx+ v v v v 09424-027 drvdd figure 27. equivalent digital output circuit 09424-028 sclk, pdwn, o r stby 30k? 350? a v dd1 figure 28. equivalent sclk, pdwn, or stby input circuit 09424-029 reset 350 ? a v dd2 figure 29. equivalent reset input circuit
ad9278 rev. 0 | page 18 of 44 c sb 70k ? 350? avdd1 a v dd1 0 9424-030 figure 30. equivalent csb input circuit vref 6k ? 09424-031 a v dd2 figure 31. equivalent vref circuit 09424-032 100 ? a v dd2 rbias figure 32. equivale nt rbias circuit gain+ 50? a vdd2 09424-033 figure 33. equivalent gain+ input circuit g ain? 50? 70k ? avdd2 0.8 v 09424-034 figure 34. equivalent gain? input circuit c wx+, cwx? avdd2 09424-035 figure 35. equivalent cw i, cwq output circuit gpox 10? a v dd2 09424-036 figure 36. equivalent gpox output circuit
ad9278 rev. 0 | page 19 of 44 ultrasound theory of operation beamformer central control rx beamformer (b and f modes) color doppler (pw) processing (f mode) image and motion processing (b mode) spectral doppler processing mode display audio output tx beamformer cw (analog) beamformer transducer array 128, 256, ... elements bidirectional cable hv mux/ demux t/r switches tx hv amplifiers multichannels ad9278 aaf vga lna adc 09424-037 figure 37. simplified ultrasound system block diagram the primary application for the ad9278 is medical ultrasound. figure 37 shows a simplified block diagram of an ultrasound system. a critical function of an ultrasound system is the time gain control (tgc) compensation for physiological signal attenuation. because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-db vga is the optimal solution. key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an adc. because ultrasound machines use beamforming techniques requiring large binary-weighted numbers of channels (for example, 32 to 512), using the lowest power at the lowest possible noise is of chief importance. most modern ultrasound machines use digital beamforming. in this technique, the signal is converted to digital format immediately following the tgc amplifier, and then beam- forming is accomplished digitally. the adc resolution of 12 bits with up to 50 msps sampling satisfies the requirements of both general-purpose and high end systems. the power dissipation of the adc scales with programmable speed modes for optimum power performance depending on system architecture. power conservation, high performance, and low cost are three of the most important factors in low end and portable ultra- sound machines, and the ad9278 is designed to meet these criteria. for additional information regarding ultrasound systems, see how ultrasound system considerations influence front-end component choice, analog dialogue , volume 36, number 3, mayCjuly 2002, and the ad9271a revolutionary solution for portable ultrasound, analog dialogue , volume 41, number 7, july 2007.
ad9278 rev. 0 | page 20 of 44 channel overview post amp lna gain? gain+ serial lvds aaf attenuator ?45db to 0db gain interpolator pipeline adc losw-x lo-x li-x lg-x reset 4lo+ 4lo? r fb2 lo generation 15.6db, 17.9db, 21.3db 21db, 24db, 27db, 30db cwi+ cwi? cwq+ cwq? doutx+ doutx? r fb1 c lg c sh transduce r c s t/r switch 09424-038 figure 38. simplified block diagram of a single channel each channel contains both a tgc signal path and a cw doppler signal path. common to both signal paths, the lna provides four user-adjustable input impedance termination options for matching different probe impedances. the cw doppler path includes an i/q demodulator with programmable phase rotation needed for analog beamforming. the tgc path includes a differential x-amp? vga, an antialiasing filter, and an adc. figure 38 shows a simplified block diagram with external components. tgc operation the tgc signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the lnas are designed to be driven from a single- ended signal source. gain values are referenced from the single- ended lna input to the differential adc input. a simple exercise in understanding the maximum and minimum gain requirements is shown in figure 39 . the maximum gain required is determined by ( adc noise floor / lna input noise floor ) + margin = 20 log(224/5.8) + 11 db = 42 db the minimum gain required is determined by ( adc input fs / lna input fs ) + margin = 20 log(2/0.45) ? 10 db = 3 db therefore, 42 db of gain range for a 12-bit, 40 msps adc with 15 mhz of bandwidth should suffice in achieving the dynamic range required for most of todays ultrasound systems. the system gain is distributed as listed in table 7 . table 7. channel gain distribution section nominal gain (db) lna 15.6/17.9/21.3 attenuator 0 to ?45 vga amplifier 21/24/27/30 filter 0 adc 0 the linear-in-db gain (law conformance) range of the tgc path is 45 db. the slope of the gain control interface is 28 db/v, and the gain control range is ?0.8 v to +0.8 v. equation 3 is the expression for the differential voltage, v gain , at the gain control interface. equation 4 is the expression for the vga attenuation, vga att , as a function of v gain . v gain (v) = ( gain+ ) ? (gain? ) (3) )8.0( v db 28)db( gain att v vga ? ?= (4) the total channel gain can then be calculated as in equation 5. gain att gain pga vga lna n channelgai ++ = )db( (5) in its default condition, the lna ha s a gain of 21.3 db (12), and the vga postamp gain is 24 db if the voltage on the gain+ pin is 0 v and the voltage on the gain? pin is 0.8 v (42 db attenu- ation). this results in a total gain (or icpt) of 3.6 db through the tgc path if the lna input is unmatched or a total gain of ?2.4 db if the lna is matched to 50 (r fb = 350 ). however, if the voltage on the gain+ pin is 1.6 v and the voltage on the gain? pin is 0.8 v (0 db attenuation), the vga gain is 24 db. this results in a total gain of 45 db through the tgc path if the lna input is unmatched or in a total gain of 39 db if the lna input is matched.
ad9278 rev. 0 | page 21 of 44 each lna output is dc-coupled to a vga input. the vga consists of an attenuator with a range of ?42 db, followed by an amplifier with 21 db/24 db/27 db/30 db of gain. the x-amp gain interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. lna full scale (0.450v p-p single-ended) lna input-referred noise floor (5.8v rms) at aaf bw = 15mhz lna + vga noise = 1.5nv/ hz a dc full scale (2v p-p) ~10db margin >11db margin adc noise floor (224v rms) minimum gain maximum gain lna adc 70db vga gain range > 45db max channel gain > 48db 88db 09424-047 figure 39. gain requirements of tgc operation for a 12-bit, 40 msps adc
ad9278 rev. 0 | page 22 of 44 table 8. sensitivity and dynamic range of trade-offs 1 , 2 , 3 lna vga channel gain typical output dynamic range (db) (v/v) (db) full-scale input (v p-p) input noise (nv/hz) postamp gain (db) gain+ = 0 v 4 gain+ = 1.6 v 5 input-referred noise 6 at gain+ = 1.6 v (nv/hz) 6 15.6 0.733 1.60 21 68.6 63.6 1.863 24 67.8 61.2 1.773 27 66.5 58.5 1.725 30 64.7 55.7 1.701 7.8 17.9 0.550 1.42 21 68.6 62.6 1.590 24 67.8 60.0 1.531 27 66.5 57.3 1.500 30 64.7 54.4 1.485 11.6 21.3 0.367 1.27 21 68.6 60.6 1.347 24 67.8 57.9 1.316 27 66.5 55.0 1.301 30 64.7 52.1 1.293 1 lna: output full scale = 4.4 v p-p differential. 2 filter: loss ~ 1 db, nbw = 13.3 mhz, gain? = 0.8 v. 3 adc: 40 msps, 70 db snr, 2 v p-p full-scale input. 4 output dynamic range at minimum vga gain (vga dominated). 5 output dynamic range at maximum vga gain (lna dominated). 6 channel noise at maximum vga gain. table 8 demonstrates the sensitivity and dynamic range of trade-offs that can be achieved relative to various lna and vga gain settings. for example, when the vga is set for the minimum gain voltage, the tgc path is dominated by vga noise and achieves the maximum output snr. however, as the postamp gain options are increased, the input-referred noise is reduced and the snr is degraded. if the vga is set for the maximum gain voltage, the tgc path is dominated by lna noise and achieves the lowest input- referred noise but with degraded output snr. the higher the tgc (lna + vgc) gain, the lower the output snr. as the postamp gain is increased, the input-referred noise is reduced. at low gains, the vga should limit the system noise performance (snr); at high gains, the noise is defined by the source and the lna. the maximum voltage swing is bound by the full-scale peak-to-peak adc input voltage (2 v p-p). both the lna and vga have full-scale limitations within each section of the tgc path. these limitations are dependent on the gain setting of each function block and on the voltage applied to the gain+ and gain? pins. the lna has three limitations, or full-scale settings, that can be applied through the spi. similarly, the vga has four postamp gain settings that can be applied through the spi. the voltage applied to the gain pins determines which amplifier (the lna or vga) saturates first. the maximum signal input level prior to 0.1 db compression on the output of the lna that can be applied as a function of voltage on the gain pins for the selectable gain options of the spi is shown in figure 40 to figure 42 . 1.2 0.8 1.0 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 gain+ (v) input full scale (v p-p) 09424-048 pga gain = 21db pga gain = 24db pga gain = 27db pga gain = 30db figure 40. lna with 15.6 db gain setting/vga full-scale limitations
ad9278 rev. 0 | page 23 of 44 0.6 0.7 0.8 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 gain+ (v) input full scale (v p-p) 09424-049 pga gain = 21db pga gain = 24db pga gain = 27db pga gain = 30db figure 41. lna with 17.9 db gain setting/vga full-scale limitations 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 input full scale (v p-p) gain+ (v) pga gain = 21db pga gain = 30db 09424-050 pga gain = 27db pga gain = 24db figure 42. lna with 21.3 db gain setting/vga full-scale limitations low noise amplifier (lna) good system sensitivity relies on a proprietary ultralow noise lna at the beginning of the signal chain, which minimizes the noise contribution in the following vga. active impedance control optimizes noise performance for applications that benefit from input impedance matching. the lna input, li-x, is capacitively coupled to the source. an on-chip bias generator establishes dc input bias voltages of approximately 2.2 v and centers the output common-mode levels at 1.5 v (avdd2 divided by 2). a capacitor, c lg , of the same value as the input coupling capacitor, c s , is connected from the lg-x pin to ground. it is highly recommended that the lg-x pins form a kelvin type connection to the input or probe connection ground. simply connecting the lg-x pin to ground near the device can allow differences in potential to be amplified through the lna. this generally shows up as a dc offset voltage that can vary from channel to channel and part to part depending on the appli- cation and the layout of the pcb. the lna supports a nominal differential output voltage of 4.4 v p-p with positive and negative excursions of 1.1 v from a common-mode voltage of 1.5 v. the lna differential gain sets the maximum input signal before saturation. one of three gains is set through the spi. overload protection ensures quick recovery time from large input voltages. because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the esd protection. low value feedback resistors and the current-driving capability of the output stage allow the lna to achieve a low input- referred noise voltage of 1.3 nv/hz (at a gain of 21.3 db). on- chip resistor matching results in precise single-ended gains, which are critical for accurate impedance control. the use of a fully differential topology and negative feedback minimizes distortion. low second-order harmonic distortion is particularly important in second harmonic ultrasound imaging applications. differential signaling enables smaller swings at each output, further reducing third-order harmonic distortion. active impedance matching the lna consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. for example, with a fixed gain of 8 (17.9 db), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, lo-x, and the positive input pin, li-x. this well-known technique is used for interfacing multiple probe impedances to a single system. the input resistance is shown in equation 1. ) 2 1( a r r fb in + = (1) where: a /2 is the single-ended gain or the gain from the li-x inputs to the lo-x outputs. r fb is the resulting impedance of the r fb1 and r fb2 combination (see figure 38 ). because the amplifier has a gain of 8 from its input to its differential output, it is important to note that the gain, a/2, is the gain from pin li-x to pin lo-x and that it is 6 db less than the gain of the amplifier, or 12.1 db (4). the input resistance is reduced by an internal bias resistor of 15 k in parallel with the source resistance connected to pin li-x, with pin lg-x ac grounded. equation 2 can be used to calculate the required r fb for a desired r in , even for higher values of r in . + = k15|| )41( fb in r r (2) for example, to set r in to 200 , the value of r fb must be 1000 . if the simplified equation (equation 2) is used to calculate r in , the value is 194 , resulting in a gain error of less than 0.27 db. some factors, such as the presence of a dynamic source resistance, may influence the absolute gain accuracy more significantly. at higher frequencies, the input capacitance of the lna must be considered. the user must determine the level of matching accuracy and adjust r fb accordingly.
ad9278 rev. 0 | page 24 of 44 the bandwidth (bw) of the lna is greater than 100 mhz. ultimately, the bw of the lna limits the accuracy of the synthesized r in . for r in = r s up to about 200 , the best match is between 100 khz and 10 mhz, where the lower frequency limit is determined by the size of the ac coupling capacitors, and the upper limit is determined by the lna bw. furthermore, the input capacitance and r s limit the bw at higher frequencies. figure 43 shows r in vs. frequency for various values of r fb . 09424-040 10 100 1k 100k 1m 10m 100m input resistance ( ? ) frequency (hz) r s = 50 ? , r fb = 200 ? , c sh = 70pf r s = 100 ? , r fb = 400 ? , c sh = 20pf r s = 200 ? , r fb = 800 ? r s = 500 ? , r fb = 2k ? figure 43. r in vs. frequency for various values of r fb (effects of r sh and c sh are also shown) note that, at the lowest value of r in (50 ), r in peaks at frequencies greater than 10 mhz. this is due to the bw roll-off of the lna. however, as can be seen for larger r in values, parasitic capaci- tance starts rolling off the signal bw before the lna can produce peaking. c sh further degrades the match; therefore, c sh should not be used for values of r in that are greater than 100 . table 9 lists the recommended values for r fb and c sh in terms of r in . c fb is needed in series with r fb because the dc levels at pin lo-x and pin li-x are unequal. table 9. active termination external component values lna gain (db) r in () r fb () minimum c sh (pf) bw (mhz) 15.6 50 200 90 57 17.9 50 250 70 69 21.3 50 350 50 88 15.6 100 400 30 57 17.9 100 500 20 69 21.3 100 700 10 88 15.6 200 800 n/a 72 17.9 200 1000 n/a 72 21.3 200 1400 n/a 72 lna noise the short-circuit noise voltage (input-referred noise) is an important limit on system performance. the short-circuit noise voltage for the lna is 1.3 nv/hz at a gain of 21.3 db, including the vga noise at a vga postamp gain of 27 db. these measure- ments, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (nf) performance of the configurations shown in figure 44 . v out unterminated + ? li-x r in r s v out shunt termination + ? li-x r in r s r s v out active termination + ? li-x r in r fb r fb 1 + a/2 r s r in = 09424-041 figure 44. input configurations figure 45 and figure 46 are simulations of noise figure vs. r s results using these configurations and an input-referred noise voltage of 3.5 nv/hz for the vga. unterminated (r fb = ) operation exhibits the lowest equivalent input noise and noise figure. figure 46 shows the noise figure vs. source resistance rising at low r s where the lna voltage noise is large compared with the source noiseand at high r s due to the noise contribution from r fb . the lowest nf is achieved when r s matches r in . the main purpose of input impedance matching is to improve the transient response of the system. with shunt termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the lna input voltage noise generator. with active termination, however, the contributions of both are smaller (by a factor of 1/(1 + lna gain)) than they would be for shunt termination. figure 45 shows the relative noise figure performance. with an lna gain of 21.3 db, the input impedance was swept with r s to preserve the match at each point. the noise figures for a source impedance of 50 are 7.3 db, 4.2 db, and 2.8 db for the shunt termination, active termination, and unterminated configurations, respectively. the noise figures for 200 are 4.5 db, 1.7 db, and 1.0 db, respectively. figure 46 shows the noise figure as it relates to r s for various values of r in , which is helpful for design purposes.
ad9278 rev. 0 | page 25 of 44 10 100 1k 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 r s ( ? ) noise figure (db) unterminated shunt termination active termination 09424-042 figure 45. noise figure vs. r s for shunt termination, active termination matched and unterminated inputs, v gain = 1.6 v 10 100 1k 0 1 2 3 4 5 6 7 8 r s ( ? ) noise figure (db) 09424-043 r in = 50 ? r in = 75 ? r in = 100 ? r in = 200 ? unterminated figure 46. noise figure vs. r s for various fixed values of r in , active termination matched inputs, v gain = 1.6 v input overdrive excellent overload behavior is of primary importance in ultrasound. both the lna and vga have built-in overdrive protection and quickly recover after an overload event. as with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. figure 47 shows a simplified ultrasound transducer interface. a common transducer element serves the dual functions of transmitting and receiving ultrasound energy. during the transmitting phase, high voltage pulses are applied to the ceramic elements. a typical transmit/receive (t/r) switch can consist of four high voltage diodes in a bridge configuration. although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and the resulting leakage transients imposed on the li-x inputs can be problematic. the external input overload protection scheme also contains a pair of back-to-back signal diodes that should be in place prior to the ac coupling capacitors. keep in mind that all diodes are prone to exhibiting some amount of shot noise. many types of diodes are available for achieving the desired noise performance. the configuration shown in figure 47 tends to add 2 nv/hz of input-referred noise. decreasing the 5 k resistor and increasing the 2 k resistor may improve noise contribution, depending on the application. with the diodes shown in figure 47 , clamping levels of 0.5 v or less significantly enhance the overload performance of the system. because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. overload can occur in the preamplifier and in the vga. immediately following a transmit pulse, the typical vga gains are low, and the lna is subject to overload from t/r switch leakage. with increasing gain, the vga can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. transducer 10nf 10nf 2k? 5k? 5k? ad9278 tx driver hv +5 v ?5v lna 09424-044 figure 47. input overload protection
ad9278 rev. 0 | page 26 of 44 variable gain amplifier (vga) the differential x-amp vga provides precise input attenu- ation and interpolation. it has a low input-referred noise of 3.5 nv/hz and excellent gain linearity. the vga is driven by a fully differential input signal from the lna. the x-amp archi- tecture produces a linear-in-db gain law conformance and low distortion levelsonly deviating 0.5 db or less from the ideal. the gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. the resulting total gain range is 45 db, which allows for range loss at the endpoints. the x-amp inputs are part of a programmable gain feedback amplifier (pga) that completes the vga. the pga in the vga can be programmed to a gain of 21 db, 24 db, 27 db, or 30 db. this allows for optimization of channel gain for different imaging modes in the ultrasound system. the vga bandwidth is approximately 100 mhz. the input stage is designed to ensure excellent frequency response uniformity across the gain setting. for tgc mode, this minimizes time delay variation across the gain range. gain control the gain control interface, gain, is a differential input. v gain varies the gain of all vgas through the interpolator by selecting the appropriate input stages connected to the input attenuator. for gain? at 0.8 v, the nominal gain+ range for 28 db/v is 0 v to 1.6 v, with the best gain linearity from approximately 0.16 v to 1.44 v, where the error is typically less than 0.5 db. for gain+ voltages greater than 1.44 v and less than 0.16 v, the error increases. the value of gain+ can exceed the supply voltage by 1 v without gain foldover. gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. there are two ways in which the gain+ and gain? pins can be interfaced. using a single-ended method, a kelvin type of connection to ground can be used, as shown in figure 48 . for driving multiple devices, it is preferable to use a differential method, as shown in figure 49 . in either method, the gain+ and gain? pins should be dc-coupled and driven to accom- modate a 1.6 v full-scale input. gain+ gain? 100 ? ad9278 0v to 1.6v dc 0.01f 0.01f kelvin connection 09424-052 figure 48. single-ended gain pin configuration 09424-053 ad8138 499 ? ad9278 499 ? 0.4v dc at 0.8v cm 0.8v dc 0.4v dc at 0.8v cm 499? a v dd2 0.8v cm 523 ? 100 ? 0.01f gain+ gain? 0.01f 100 ? 31.3k ? 10k? figure 49. differential gain pin configuration vga noise in a typical application, a vga compresses a wide dynamic range input signal to within the input span of an adc. the input-referred noise of the lna limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the vga, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. this latter limit is set in accordance with the total noise floor of the adc. output-referred noise as a function of gain+ is shown in figure 7 , figure 8 , and figure 10 for the short-circuit input conditions. the input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. the output-referred noise is a flat 50 nv/hz (postamp gain = 24 db) over most of the gain range because it is dominated by the fixed output-referred noise of the vga. at the high end of the gain control range, the noise of the lna and of the source prevail. the input-referred noise reaches its minimum value near the maximum gain control voltage, where the input- referred contribution of the vga is miniscule. at lower gains, the input-referred noise and, therefore, the noise figure, increases as the gain decreases. the instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. the contribution of the adc noise floor has the same depen- dence. the important relationship is the magnitude of the vga output noise floor relative to that of the adc. gain control noise is a concern in very low noise applications. thermal noise in the gain control interface can modulate the channel gain. the resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. the gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 mhz. care should be taken to minimize noise impinging at the gain inputs. an external rc filter can be used to remove v gain source noise. the filter bandwidth should be sufficient to accommodate the desired control bandwidth. antialiasing filter (aaf) the filter that the signal reaches prior to the adc is used to reject dc signals and to band limit the signal for antialiasing. the antialiasing filter is a combination of a single-pole high- pass filter and a second-order low-pass filter. the high-pass filter can be configured at a ratio of the low-pass filter cutoff. this is selectable through the spi. the filter uses on-chip tuning to trim the capacitors and, in turn, to set the desired cutoff frequency and reduce variations. the default ?3 db low-pass filter cutoff is 1/3 or 1/4.5 the adc sample clock rate. the cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the spi. the cutoff tolerance is maintained from 8 mhz to 18 mhz.
ad9278 rev. 0 | page 27 of 44 tuning is normally off to avoid changing the capacitor settings during critical times. the tuning circuit is enabled and disabled through the spi. initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or adc sample rate. occasional retuning during an idle time is recommended to compensate for temperature drift. a total of eight spi-programmable settings allows the user to vary the high-pass filter cutoff frequency as a function of the low-pass cutoff frequency. two examples are shown in tabl e 10 : one is for an 8 mhz low-pass cutoff frequency, and the other is for an 18 mhz low-pass cutoff frequency. in both cases, as the ratio decreases, the amount of rejection on the low-end fre- quencies increases. therefore, making the entire aaf frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing. table 10. spi-selectable high-pass filter cutoff options high-pass cutoff frequency spi setting ratio 1 low-pass cutoff = 8 mhz low-pass cutoff = 18 mhz 0 12.00 670 khz 1.5 mhz 1 8.57 930 khz 2.1 mhz 2 6.67 1.2 mhz 2.7 mhz 3 5.46 1.47 mhz 3.3 mhz 4 4.62 1.73 mhz 3.9 mhz 5 4.00 2.0 mhz 4.5 mhz 6 3.53 2.27 mhz 5.1 mhz 7 3.16 2.53 mhz 5.7 mhz 1 ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency. adc the ad9278 uses a pipelined adc architecture. the quantized output from each stage is combined into a 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. sampling occurs on the rising edge of the clock. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and output clocks. clock input considerations for optimum performance, the ad9278 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 50 shows the preferred method for clocking the ad9278. a low jitter clock source, such as the valpey fisher oscillator, vfac3-bhl-50 mhz, is converted from single-ended to differ- ential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the ad9278 to approximately 0.8 v p-p differential. this helps to prevent the large voltage swings of the clock from feeding through to other portions of the ad9278, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 3.3 v 50? 100 ? clk? clk+ ad9278 mini-circuits ? adt1-1wt, 1:1z xfmr vfac3 out 0 9424-055 figure 50. transformer-coupled differential clock if a low jitter clock is available, another option is to ac-couple a differential pecl signal to the sample clock input pins, as shown in figure 51 . the ad951x family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad951x family clk clk *50 ? resistor is optional. pecl driver 3.3 v out vfac3 09424-056 clk? clk+ ad9278 50? * figure 51. differential pecl sample clock 100 ? 0.1f 0.1f 0.1f 0.1f ad951x family clk clk *50 ? resistor is optional. lvds driver 3.3 v out vfac3 09424-057 clk? clk+ ad9278 50? * figure 52. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 53 ). although the clk+ input circuit supply is avdd1 (1.8 v), this input is designed to withstand input voltages of up to 3.3 v, making the selection of the drive logic voltage very flexible. 0.1f optional 100 ? 0.1f 0.1f 39k? cmos driver 0.1f clk clk *50 ? resistor is optional. ad951x family 3.3 v out vfac3 09424-058 clk? clk+ ad9278 50? * figure 53. single-ended 1.8 v cmos sample clock
ad9278 rev. 0 | page 28 of 44 0.1f 0.1f 0.1f cmos driver optional 100 ? 0.1f clk clk *50 ? resistor is optional. ad951x family 3.3 v out vfac3 09424-059 clk? clk+ ad9278 50 ? * figure 54. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9278 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9278. when the dcs is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see table 18 for more details on using this feature. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated as follows: snr degradation = 20 log 10(1/2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter (see figure 55 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9278. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources, such as the valpey fisher vfac3 series. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about how jitter performance relates to adcs (visit www.analog.com ). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 09424-060 0.25ps figure 55. ideal snr vs. input frequency and jitter power dissipation and power-down mode as shown in figure 56 and figure 57 , the power dissipated by the ad9278 is proportional to its sample rate. the digital power dissipation does not vary significantly because it is determined primarily by the drvdd supply and the bias current of the lvds output drivers. 250 200 150 100 50 0 01020304050 sampling frequency (msps) currents (ma) 09424-061 mode iii, f sample = 50msps i drvdd mode ii, f sample = 25msps mode i, f sample = 40msps figure 56. supply current vs. f sample for f in = 5 mhz 110 105 100 95 90 85 80 75 70 65 60 01020304050 sampling frequency (msps) power/channel (mw/ch) 09424-062 mode iii, f sample = 50msps mode ii, f sample = 25msps mode i, f sample = 40msps figure 57. power per channel vs. f sample for f in = 5 mhz the ad9278 features scalable lna bias currents (see table 18 , register 0x12). the default lna bias current settings are high.
ad9278 rev. 0 | page 29 of 44 figure 58 shows the typical reduction of avdd2 current with each bias setting. it is also recommended that the lna offset be adjusted using register 0x10 (see table 18 ) when the lna bias setting is low. high mid-high mid-low low 102 104 106 108 110 112 114 116 118 total avdd2 current (ma) lna bias setting 09424-063 figure 58. avdd2 current at different lna bias settings, f sample = 40 msps by asserting the pdwn pin high, the ad9278 is placed into power-down mode. in this state, the device typically dissipates 5 mw. during power-down, the lvds output drivers are placed into a high impedance state. the ad9278 returns to normal operating mode when the pdwn pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. by asserting the stby pin high, the ad9278 is placed into a standby mode. in this state, the device typically dissipates 420 mw. during standby, the entire part is powered down except the internal references. the lvds output drivers are placed into a high impedance state. this mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. the time to power the device back up is also greatly reduced. the ad9278 returns to normal operating mode when the stby pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. in power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on vref are discharged when entering power-down mode and must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. to restore the device to full operation, approximately 0.5 ms is required when using the recommended 1 f and 0.1 f decoupling capacitors on the vref pin and the 0.01 f decoupling capacitors on the gain pins. most of this time is dependent on the gain decoupling: higher value decoupling capacitors on the gain pins result in longer wake-up times. a number of other power-down options are available when using the spi port interface. the user can individually power down each channel or put the entire device into standby mode. this allows the user to keep the internal pll powered up when fast wake-up times are required. the wake-up time is slightly dependent on gain. to achieve a 1 s wake-up time when the device is in standby mode, 0.8 v must be applied to the gain pins. see table 18 for more details on using these features. power and ground recommendations when connecting power to the ad9278, it is recommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (drvdd). if only one 1.8 v supply is available, it should be routed to the avdd1 pin first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd pin. the user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. locate these capacitors close to the point of entry at the pcb level and close to the part, with minimal trace lengths. a single pcb ground plane should be sufficient when using the ad9278. with proper decoupling and smart partitioning of the analog, digital, and clock sections of the pcb, optimum perfor- mance can be easily achieved. digital outputs and timing the ad9278 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard via the spi, using register 0x14, bit 6. this lvds standard can further reduce the overall power dissipation of the device by approximately 36 mw. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9278 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point network topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination and poor differential trace routing may result in timing errors. it is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. an example of the fco (ch2), dco (ch1), and data (ch3) stream with proper trace length and position is shown in figure 59 .
ad9278 rev. 0 | page 30 of 44 09424-064 ch1 500mv/div = dco ch2 500mv/div = data ch3 500mv/div = fco 5.0ns/div figure 59. lvds output timing example in ansi-644 mode (default) an example of the lvds output using the ansi-644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 24 inches on regular fr-4 material is shown in figure 60 . figure 61 shows an example of the trace lengths exceeding 24 inches on regular fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (and, therefore, increase the current) of all eight outputs to drive longer trace lengths (see figure 62 ). even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see figure 62 ), the power dissipation of the drvdd supply increases when this option is used. in cases that require increased driver strength to the dco and fco outputs because of load mismatch, register 0x15 allows the user to double the drive strength. to do this, set the appro- priate bit in register 0x05. note that this feature cannot be used with bits[5:4] in register 0x15 because these bits take precedence over this feature. see table 18 for more details. the format of the output data is offset binary by default. tabl e 11 provides an example of the output coding format. to change the output data format to twos complement, see the memory map section. table 11. digital output coding code (vin+) ? (vin?), input span = 2 v p-p (v) digital output offset binary (d11 to d0) 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000488 0111 1111 1111 0 ?1.00 0000 0000 0000 data from each adc is serialized and provided on a separate channel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 600 mbps (12 bits 50 msps = 600 mbps). the lowest typical conversion rate is 10 msps, but the pll can be set up for encode rates as low as 5 msps via the spi if lower sample rates are required for a specific application. see table 18 for details on enabling this feature. 09424-065 600 400 ?200 200 ?100 100 ?400 ?600 0 ?1.5ns ?0.5ns ?1.0ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (v) eye: all bits uls: 2398/2398 25 0 5 10 15 20 ?200ps ?100ps 0ps 100ps 200ps tie jitter histogram (hits) figure 60. data eye for lvds outputs in ansi-644 mode with trace lengths of less than 24 inches on standard fr-4
ad9278 rev. 0 | page 31 of 44 09424-066 400 ?300 300 ?200 200 ?100 100 ?400 0 ?1.5ns ?0.5ns ?1.0ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (v) eye: all bits uls: 2399/2399 25 0 5 10 15 20 ?200ps ?100ps 0ps 100ps 200ps tie jitter histogram (hits) figure 61. data eye for lvds outputs in ansi-644 mode with trace lengths of greater than 24 inches on standard fr-4 600 ?400 400 ?200 200 ?600 0 ?1.5ns ?0.5ns ?1.0ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (v) eye: all bits uls: 2396/2396 25 0 5 10 15 20 ?200ps ?100ps 0ps 100ps 200ps tie jitter histogram (hits) 09424-067 figure 62. data eye for lvds outputs in ansi-644 mode with 100 termination on and trace lengths of greater than 24 inches on standard fr-4
ad9278 rev. 0 | page 32 of 44 two output clocks are provided to assist in capturing data from the ad9278. dco is used to clock the output data and is equal to six times the sampling clock rate. data is clocked out of the ad9278 and must be captured on the rising and falling edges of dco, which supports double data rate (ddr) capturing. the frame clock output (fco) is used to signal the start of a new output byte and is equal to the sampling clock rate. see the timing diagram shown in figure 2 for more information. when using the serial port interface (spi), the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins if required. the default dco timing, as shown in figure 2 , is 90 relative to the output data edge. an 8-, 10-, or 14-bit serial stream can also be initiated from the spi. this allows the user to implement different serial streams and to test device compatibility with lower and higher resolution systems. when changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. when using the 14-bit option, the data stream stuffs two 0s at the end of the normal 12-bit serial data. when using the spi, all of the da ta outputs can also be inverted from their nominal state by setting bit 2 in the output_mode register (address 0x14). this is not to be confused with inverting the serial stream to an lsb first mode. in default mode, as shown in figure 2 , the msb is represented first in the data output serial stream. however, this order this can be inverted so that the lsb is represented first in the data output serial stream (see figure 3 ). there are 12 digital output test pattern options available that can be initiated through the spi. this feature is useful when validating receiver capture and timing. see tabl e 12 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns may not adhere to the data format select option. in addition, custom user-defined test patterns can be assigned in the user pattern registers (address 0x19 through address 0x1c). all test mode options except pn sequence short and pn sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver. the pn sequence short pattern produces a pseudo random bit sequence that repeats itself every 2 9 ? 1 bits, or 511 bits. a description of the pn sequence short and how it is generated can be found in section 5.1 of the itu-t o.150 (05/96) standard. the only difference is that the starting value is a specific value instead of all 1s (see table 13 for the initial values). table 12. flexible output test modes 1 output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 same yes 0010 +full-scale short 1111 1111 1111 same yes 0011 ?full-scale short 0000 0000 0000 same yes 0100 checkerboard 1010 1010 1010 0101 0101 0101 no 0101 pn sequence long n/a n/a yes 0110 pn sequence short n/a n/a yes 0111 one-/zero-word toggle 1111 1111 1111 0000 0000 0000 no 1000 user input register 0x19 and register 0x 1a register 0x1b and register 0x1c no 1001 1-/0-bit toggle 1010 1010 1010 n/a no 1010 1 sync 0000 0011 1111 n/a no 1011 one bit high 1000 0000 0000 n/a no 1100 mixed bit frequency 1010 0011 0011 n/a no 1 n/a is not applicable.
ad9278 rev. 0 | page 33 of 44 the pn sequence long pattern produces a pseudo random bit sequence that repeats itself every 2 23 ? 1 bits, or 8,388,607 bits. a description of the pn sequence long and how it is generated can be found in section 5.6 of the itu-t o.150 (05/96) standard. the only differences are that the starting value is a specific value instead of all 1s and that the ad9278 inverts the bit stream with relation to the itu-t standard (see table 13 for the initial values). table 13. pn sequence sequence initial value first three output samples (msb first) pn sequence short 0x0df 0xdf9, 0x353, 0x301 pn sequence long 0x29b80a 0x591, 0xfd7, 0x0a3 see the memory map section for information on how to change these additional digital output timing features through the spi. sdio pin this pin is required to operate the spi. it has an internal 30 k pull-down resistor that pulls this pin low and is only 1.8 v tolerant. if applications require that this pin be driven from a 3.3 v logic level, insert a 1 k resistor in series with this pin to limit the current. sclk pin this pin is required to operate the spi port interface. it has an internal 30 k pull-down resistor that pulls this pin low and is both 1.8 v and 3.3 v tolerant. csb pin this pin is required to operate the spi port interface. it has an internal 70 k pull-up resistor that pulls this pin high and is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor nominally equal to 10.0 k to ground at the rbias pin. using a resistor other than the recommended 10.0 k resistor for rbias degrades the performance of the device. therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9278. this is gained up internally by a factor of 2, setting vref to 1.0 v, which results in a full-scale differential input span of 2.0 v p-p for the adc. vref is set internally by default, but the vref pin can be driven externally with a 1.0 v reference to achieve more accuracy. however, the ad9278 does not support adc full-scale ranges below 2.0 v p-p. when applying the decoupling capacitors to the vref pin, use ceramic, low esr capacitors. these capacitors should be close to the reference pin and on the same layer of the pcb as the ad9278. the vref pin should have both a 0.1 f capacitor and a 1 f capacitor connected in parallel to the analog ground. these capacitor values are recommended for the adc to properly settle and acquire the next valid sample. the reference settings can be selected using the spi. the settings allow two options: using the internal reference or using an external reference. the internal reference option is the default setting and has a resulting differential span of 2 v p-p. table 14. spi-selectable reference settings spi-selected mode resulting vref (v) resulting differential span (v p-p) external reference n/a 2 external reference internal reference (default) 1.0 2.0 cw doppler operation each channel of the ad9278 includes a i/q demodulator. each demodulator has an individual programmable phase shifter. the i/q demodulator is ideal for phased array beamforming applica- tions in medical ultrasound. each channel can be programmed for 16 delay states/360 (or 22.5/step), selectable via the spi port. the part has a reset input used to synchronize the lo dividers of each channel. if multiple ad9278s are used, a common reset across the array ensures a synchronized phase for all channels. internal to the ad9278, the individual channel i and channel q outputs are current summed. if multiple ad9278s are used, the i and q outputs from each ad9278 can be current summed and converted to a voltage using an external transimpedance amplifier. quadrature generation the internal 0 and 90 lo phases are digitally generated by a divide-by-4 logic circuit. the divider is dc-coupled and inherently broadband; the maximum lo frequency is limited only by its switching speed. the duty cycle of the quadrature lo signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4lo input. furthermore, the divider is implemented such that the 4lo signal reclocks the final flip- flops that generate the internal lo signals and, thereby, mini- mizes noise introduced by the divide circuitry. for optimum performance, the 4lo input is driven differen- tially, as on the ad9278 evaluation board (see the ordering guide). the common-mode voltage on each pin is approx- imately 1.2 v with the nominal 3 v supply. it is important to ensure that the lo source have very low phase noise (jitter), a fast slew rate, and an adequate input level to obtain optimum performance of the cw signal chain. beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. a reset pin is provided to synchronize the lo divider circuits in different ad9278s when they are used in arrays. the reset pin resets the dividers to a known state after power is applied to multiple ad9278s. accurate channel-to-channel phase matching can only be achieved via a common pulse on the reset pin when using more than one ad9278.
ad9278 rev. 0 | page 34 of 44 ple, for a common signal applied to a pair of rf inputs of channel leads channel 1 15. phase sele e for channel-to-channel phase shift t modulator phase egister 0x2d[3:0]) i/q demodulator and phase shifter the i/q demodulators consist of double-balanced passive mixers. the rf input signals are converted into currents by transconduc- tance stages that have a maximum differential input signal capability matching the lna output full scale. these currents are then presented to the mixers, which convert them to base- band (rf ? lo) and twice rf (rf + lo). the signals are phase shifted according to the codes programmed into the spi latch (see table 15 ). the phase shift function is an integral part of the overall circuit. the phase shift listed in column 1 of table 15 is defined as being between the baseband i or q channel outputs. as an exam to an ad9278, the baseband outputs are in phase for matching phase codes. howev annel 1 is 0000 er, if the phase code for ch 2 is 0001, then channel 2 and that by 22.5. table ct cod shif i/q de (spi r 0 0000 22.5 0001 45 0010 67.5 0011 90 0100 112.5 0101 135 0110 157.5 0111 180 1000 202.5 1001 225 1010 247.5 1011 270 1100 292.5 1101 315 1110 337.5 1111 dynamic range and noise figure 63 is an interconnection block diagram of all eight channels of the ad9278. more channels are easily added to tht of b), yielding an aggregate n ; ight channels are summed, r filt and c filt are 250 and n oximately the lna gain for r filt and c filt of 2 k hile e ; 278s (4 8 = 32 channels) can be summed in ne ada4841 . summation (up to 32 when using an ada4841 as the summation amplifier) by wire-or connecting the outputs as shown. in beamforming applications, the i and q outputs of a number of receiver channels are summed. the dynamic range the system increases by the factor 10log 10 (n), where n is the number of channels (assuming random uncorrelated noise). the noise in the 8-channel example of figure 63 is increased by 9 db while the signal quadruples (18 d snr improvement of (18 ? 9) = 9 db. the output-referred noise of the cw signal path depends o the lna gain and the selection of the external summing amplifier and the value of r filt . to determine the output referred noise, it is important to know the active low-pass filter (lpf) values, r filt , and c filt , shown in figure 63 . typical filter values for a single channel are 2 k for r filt and 0.8 nf for c filt these values implement a 100 khz single-pole lpf. in the case where e 6.4 nf. if the rf and lo are offset by 10 khz, the demodulated signal is 10 khz and is passed by the lpf. the single-channel mixing gai from the rf input to the ada4841 output (for example, i1, q1) is appr and 0.8 nf. this gain can be increased by increasing the filter resistor w maintaining the corner frequency. the factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the i-to-v converter, in this example, the ada4841 . because any amplifier has limited drive capability, there is a finite number of channels that can be summed. th channel-summing limit relates directly to the current drive capability of the amplifier used to implement the active low- pass filter and current-to-voltage converter. the maximum sum, when the ada4841 is used, is 32 channels of the ad9278 that is, four ad9 o
ad9278 rev. 0 | page 35 of 44 lna lna ad7982 18-bit adc ada4841 2.5v 2.5v 4nf 10nf 10nf 50 ? 50 ? i channel a c hannel h lo generation 4 reset 4lo+ 4lo? 09424 -045 cwi+ cwi? ad9278 c filt c filt r filt 1.5v ada4841 1.5v r filt ad7982 18-bit adc ada4841 2.5v 2.5v 4nf 50 ? 50 ? q cwq+ cwq? c filt c filt r filt 1.5v ada4841 1.5v r filt figure 63. typical connection inte rface for i/q outputs in cw mode phase compensation and analog beamforming beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ultrasound transducer. beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the return- ing echo is derived. the primary application for the ad9278 i/q demodulators is in analog beamforming circuits for ultrasound cw doppler. modern ultrasound machines used for medical applications employ an array of receivers for beamforming, with typical cw doppler array sizes of up to 64 receiver channels that are phase shifted and summed together to extract coherent information. when used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor n, where n is the number of channels), whereas the noise is increased by the square root of the number of channels. this technique enhances the signal-to-noise performance of the machine. the critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. in traditional analog beamformers incorporating doppler, a v-to-i converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. the system operates at the carrier frequency (rf) through the delay line, which also sums the signals from the various channels, and then the combined signal is down- converted by an i/q demodulator. the dynamic range of the demodulator can limit the achievable dynamic range. the resultant i and q signals are filtered and then sampled by two high resolution analog-to-digital converters. the sampled signals are processed to extract the relevant doppler information. alternatively, the rf signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal, and then combining all channels. because the dynamic range expansion from beamforming occurs after demodulation, the demodulator dynamic range has little effect on the output dynamic range. the ad9278 implements this architecture. the downconversion is done by an i/q demodulator on each channel, and the summed current output is the same as in the delay line approach. the subsequent filters after the i-to-v conversion and the adcs are similar.
ad9278 rev. 0 | page 36 of 44 for cw doppler operation, the ad9278 integrates the lna, phase shifter, frequency conversion, and i/q demodulation into a single package and directly yields the baseband signal. figure 64 is a simplified diagram showing the concept for four channels. the ultrasound wave (us wave) is received by four transducer elements, te1 through te4, in an ultrasound probe and generates signals e1 through e4. in this example, the phase at te1 leads the phase at te2 by 45. in a real application, the phase difference depends on the element spacing, wavelength (), speed of sound, angle of incidence, and other factors. in figure 64 , the signals e1 through e4 are amplified by the low noise amplifiers. for optimum signal-to-noise performance, the output of the lna is applied directly to the input of the demodulators. to sum the signals e1 through e4, e2 is shifted 45 relative to e1 by setting the phase code in channel 2 to 0010, e3 is shifted 90 (0100), and e4 is shifted 135 (0110). the phase aligned current signals at the output of the ad9278 are summed in an i-to-v converter to provide the combined output signal with a theoretical improve- ment in dynamic range of 6 db for the four channels. cw application information the reset pin is used to synchronize the lo dividers in ad9278 arrays. because they are driven by the same internal lo, the four channels in any ad9278 are inherently synchronous. however, when multiple ad9278s are used, it is possible that their dividers wake up in different phase states. the function of the reset pin is to phase align all the lo signals in multiple ad9278s. the 4lo divider of each ad9278 can be initiated in one of four possible states: 0, 90, 180, and 270 relative to other ad9278s. the internally generated i/q signals of each ad9278 lo are always at a 90 angle relative to each other, but a phase shift can occur during power-up between the dividers of multiple ad9278s used in a common array. the reset mechanism also allows the measurement of non- mixing gain from the rf input to the output. the rising edge of the active high reset pulse can occur at any time; however, the duration should be 20 ns minimum. when the reset pulse transitions from high to low, the lo dividers are reactivated on the next rising edge of the 4lo clock. to guarantee synchronous operation of an array of ad9278s, the reset pulse must go low on all devices before the next rising edge of the 4lo clock. therefore, it is best to have the reset pulse go low on the falling edge of the 4lo clock; at the very least, the t setup should be 5 ns. an optimal timing setup is for the reset pulse to go high on a 4lo falling edge and to go low on a 4lo falling edge; this gives 15 ns of setup time even at a 4lo frequency of 32 mhz (8 mhz internal lo). use the following procedure to check the synch- ronization of multiple ad9278s: 1. activate at least one channel per ad9278 by setting the appropriate channel enable bit in the serial interface. 2. set the phase code of all ad9278 channels to the same logic state, for example, 0000. 3. apply the same test signal to all devices to generate a sine wave in the baseband output and measure the output of one channel per device. 4. apply a reset pulse to all ad9278s. 5. because all phase codes of the ad9278s should be the same, the combined signal of multiple devices should be n times greater than a single channel. if the combined signal is less than n times one channel, one or more of the lo phases of the individual ad9278s are in error. s1 s2 s3 s4 e1 e2 e3 e4 90 45 135 0 summed output s1 + s2 + s3 + s4 s1 through s4 are now in phase phase bit settings channel 1 phase set for 135 lag channel 2 phase set for 90 lag channel 3 phase set for 45 lag channel 4 phase set for 0 lag transduce r element te1 through element te4 convert us waves to electrical signals lna lna lna lna 4 us waves are delayed 45 each with respect to each other 09424-046 figure 64. simplified example of the ad9278 phase shifter
ad9278 rev. 0 | page 37 of 44 serial port interface (spi) the ad9278 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, as documented in the memory map section. detailed operational information can be found in the an-877 application note, interfacing to high speed adcs via spi . three pins define the serial port interface, or spi: sclk, sdio, and csb (see table 16). the sclk (serial clock) pin is used to synchronize the read and write data presented to the device. the sdio (serial data input/output) pin is a dual-purpose pin that allows data to be sent to and read from the internal memory map registers of the device. the csb (chip select bar) pin is an active low control that enables or disables the read and write cycles. table 16. serial port pins pin function sclk serial clock. serial shift cl ock input. sclk is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. dual-purpose pin that typically serves as an inp ut or an output, depending on the instruction sent and the relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of csb in conjunction with the rising edge of sclk determines the start of the framing sequence. during an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by bit field w0 and bit field w1. an example of the serial timing and its defini- tions can be found in figure 66 and table 17. during normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to execute instructions. normally, csb remains low until the communication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory transfers without the need for additional instructions. regardless of the mode, if csb is taken high in the middle of a byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port can be configured to operate in different manners. for applications that do not require a control port, the csb line can be tied and held high. this places the remainder of the spi pins in their secondary mode, as defined in the sdio pin and sclk pin sections. csb can also be tied low to enable 2-wire mode. when csb is tied low, sclk and sdio are the only pins required for communication. although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the csb line. when operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and to read the contents of the on-chip memory. if the instruction is a read- back operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb firs t mode or lsb first mode. msb first mode is the default at power-up and can be changed by adjusting the configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . hardware interface the pins described in table 16 constitute the physical interface between the users programming device and the serial port of the ad9278. the sclk and csb pins function as inputs when using the spi. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdio pins share a common connection, ensure that proper v oh levels are met. figure 65 shows the number of sdio pins that can be connected together and the resulting v oh level, assuming the same load for each ad9278. 09424-068 number of sdio pins connected together v oh (v) 1.715 1.720 1.725 1.730 1.735 1.740 1.745 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 03 0 2010 40 50 60 70 80 90 100 figure 65. sdio pin loading
ad9278 rev. 0 | page 38 of 44 this interface is flexible enough to be controlled by either serial proms or pic microcontrollers, providing the user with an alternative method, other than a full spi controller, for programming the device (see the an-812 application note). don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t high t clk t low t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 09424-069 figure 66. serial timing details table 17. serial timing definitions parameter timing (ns min) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t high 16 minimum period that sclk should be in a logic high state t low 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 66 ) t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 66 )
ad9278 rev. 0 | page 39 of 44 memory map reading the memory map table each row in the memory map register table has eight bit loca- tions. the memory map is roughly divided into three sections: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0x04 to address 0xff), and the program register map (address 0x08 to address 0x2d). the leftmost column of the memory map indicates the register address, and the default value is shown in the second rightmost column. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, address 0x09, the clock register, has a default value of 0x01, meaning that bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 0 of this address, followed by 0x01 in register 0xff (the transfer bit), the duty cycle stabilizer is turned off. it is important to follow each writing sequence with a transfer bit to update the spi registers. all registers except register 0x00, register 0x04, register 0x05, and register 0xff are buffered with a master slave latch and require writing to the transfer bit. for more information on this and other functions, consult the an-877 application note, interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values after a reset, critical registers are automatically loaded with default values. these values are indicated in table 18 , where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, bit is cleared is synonymous with bit is set to logic 0 or writing logic 0 for the bit.
ad9278 rev. 0 | page 40 of 44 table 18. ad9278 memory map registers addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value comments chip configuration registers 0x00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 nibbles should be mirrored so that lsb or msb first mode is set cor- rectly regardless of shift mode. 0x01 chip_id chip id bits[7:0] (ad9278 = 0x7d), (default) 0x7d default is unique chip id, different for each device. read-only register. 0x02 chip_grade x x speed mode[5:4] (identify device variants of chip id) 00: mode i (40 msps) (default) 01: mode ii (25 msps) 10: mode iii (50 msps) x x x x 0x00 child id used to differentiate adc speed power modes. device index and transfer registers 0x04 device_index_2 x x x x data channel h 1 = on (default) 0 = off data channel g 1 = on (default) 0 = off data channel f 1 = on (default) 0 = off data channel e 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. 0x05 device_index_1 x x clock channel dco 1 = on 0 = off (default) clock channel fco 1 = on 0 = off (default) data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. 0xff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. program function registers 0x08 modes x x x 0 0 internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = cw mode (tgc pdwn) 0x00 determines generic modes of chip operation (global). 0x09 clock x x x x x x x dcs 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer (dcs) on and off (global). 0x0d test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test modesee table 12 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn sequence long 0110 = pn sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0x00 when this register is set, the test data is placed on the output pins in place of normal data. (local, expect for pn sequence.) 0x0e gpo outputs x x x x general-purpose digital outputs 0x00 values placed on gpo[0:3] pins (global).
ad9278 rev. 0 | page 41 of 44 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value comments 0x0f flex_channel_ input filter cutoff frequency control 0000 = 1.3 1/3 f sample 0001 = 1.2 1/3 f sample 0010 = 1.1 1/3 f sample 0011 = 1.0 1/3 f sample (default) 0100 = 0.9 1/3 f sample 0101 = 0.8 1/3 f sample 0110 = 0.7 1/3 f sample 1000 = 1.3 1/4.5 f sample 1001 = 1.2 1/4.5 f sample 1010 = 1.1 1/4.5 f sample 1011 = 1.0 1/4.5 f sample 1100 = 0.9 1/4.5 f sample 1101 = 0.8 1/4.5 f sample 1110 = 0.7 1/4.5 f sample x x x x 0x30 antialiasing filter cutoff (global). 0x10 flex_offset x x 1 0 0 0 0 0 0x20 reserved. 0x11 flex_gain x x x x pga gain 00 = 21 db 01 = 24 db (default) 10 = 27 db 11 = 30 db lna gain 00 = 15.6 db 01 = 17.9 db 10 = 21.3 db (default) 0x06 lna and pga gain adjustment (global). 0x12 bias_current x x x x 1 x lna bias 00 = high 01 = mid-high (default) 10 = mid-low 11 = low 0x09 lna bias current adjustment (global). 0x14 output_mode x 0 = lvds ansi-644 (default) 1 = lvds low power, (ieee 1596.3 similar) x x x output invert enable 1 = on 0 = off (default) data format select 00 = offset binary (default) 01 = twos complement 0x00 configures the outputs and the format of the data (bits[7:3] and bits[1:0] are global; bit 2 is local). 0x15 output_adjust x x output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 x x x dco and fco 2 drive strength 1 = on 0 = off (default) 0x00 determines lvds or other output properties. primarily functions to set the lvds span and common-mode levels in place of an external resistor (bits[7:1] are global; bit 0 is local). 0x16 output_phase x x x x output clock phase adjust 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge (default) 0100 = reserved 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = reserved 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge 0x03 on devices that use global clock divide, deter- mines which phase of the divider output is used to supply the output clock. internal latching is unaffected. (global) 0x18 flex_vref x 0 = internal reference 1 = external reference x x x x 1 1 0x03 select internal reference (recommended default) or external reference (global). 0x19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern 1, lsb (global).
ad9278 rev. 0 | page 42 of 44 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value comments 0x1a user_patt1_msb b15 b14 b13 b 12 b11 b10 b9 b8 0x00 user-defined pattern 1, msb (global). 0x1b user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern 2, lsb (global). 0x1c user_patt2_msb b15 b14 b13 b 12 b11 b10 b9 b8 0x00 user-defined pattern 2, msb (global). 0x21 serial_control lsb first 1 = on 0 = off (default) x x x <10 msps, low encode rate mode 1 = on 0 = off (default) 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 serial stream control (global). 0x22 serial_ch_stat x x x x x x channel output reset 1 = on 0 = off (default) channel power- down 1 = on 0 = off (default) 0x00 used to power down individual sections of a converter (local). 0x2b flex_filter x enable automatic low-pass tuning 1 = on (self- clearing) x x high-pass filter cutoff 0000 = f lp /12.00 0001 = f lp /8.57 0010 = f lp /6.67 0011 = f lp /5.46 0100 = f lp /4.62 0101 = f lp /4.00 0110 = f lp /3.53 0111 = f lp /3.16 0x00 filter cutoff (global). (f lp = low-pass filter cutoff frequency.) 0x2c analog_input x x x x x x lo-x, losw-x connection 00 = r fb1 01 = r fb1 || rfb2 10 = r fb2 11 = 0x00 lna active termination/input impedance (global). 0x2d cw doppler i/q demodulator phase x x x cw doppler channel enable 1 = on 0 = off i/q demodulator phase 0000 = 0 0001 = 22.5 0010 = 45 0011 = 67.5 0100 = 90 0101 = 112.5 0110 = 135 0111 = 157.5 1000 = 180 1001 = 202.5 1010 = 225 1011 = 247.5 1100 = 270 1101 = 292.5 1110 = 315 1111 = 337.5 0x00 phase of demodulators (local).
ad9278 rev. 0 | page 43 of 44 outline dimensions * compliant with jedec standards mo-275-eeab-1 with exception to package height. 10-21-2010-b 0.80 0.60 ref a b c d e f g 9 10 8 11 12 7 5 642 31 bottom view 8.80 bsc sq h j k l m detail a top view detail a coplanarity 0.20 0.50 0.45 0.40 * 1.40 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.25 min 0.65 min figure 67. 144-ball chip scale package, ball grid array [csp_bga] (bc-144-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9278-BBCZ ?40c to +85c 144-ball chip scale package, ball grid array [csp_bga] bc-144-1 ad9278-50ebz evaluation board 1 z = rohs compliant part.
ad9278 rev. 0 | page 44 of 44 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09424-0-10/10(0)

▲Up To Search▲

Price & Availability of AD9278-BBCZ

	To Download AD9278-BBCZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .